1. Field of the Invention
The present invention relates to user re-programmable interconnect architectures, which employ active devices as re-programmable interconnect elements whose programmed state is stored in an active storage element (typically a static RAM cell). More particularly, the present invention relates to such architectures employing fewer storage elements than reprogrammable interconnect elements and which employ decoding to activate individual interconnect paths.
2. The Prior Art
User-programmable interconnect integrated circuit architectures are known in the art. These architectures typically comprise a set of interconnect conductors in an integrated circuit which a user may programmably connect to one another by the use of programmable elements.
The prior art contains examples of such architectures using one-time programmable interconnect elements, such as antifuses. A typical example of an architecture employing one-time programmable antifuse elements is disclosed in U.S. Pat. No. 4,758,745. The prior art contains examples of such architectures using re-programmable interconnect elements, such as active switching devices, each of whose programmed state (i.e., "on" or "off") is stored in an associated active storage element (typically a static RAM cell). A typical example of such an architecture is disclosed in U.S. Pat. No. 4,870,302.
While prior art user re-programmable interconnect architectures have found application in a number of different devices, such as field-programmable gate array devices, they are inherently limited by the amount of area which must be taken up on the integrated circuit die to accommodate the active switching device, usually an N-channel pass transistor or a CMOS pass transistor pair, and its associated active storage element. Because of this area utilization necessary to accommodate the interconnect mechanism, the size of practically-realizable re-programmable interconnect architectures is limited.
Bipolar crosspoint switch implementations of such user-programmable interconnect integrated circuit architectures are known in the art. For example, H. Shin et al, "A 5Gb/s 16.times.16 Si-Bipolar Crosspoint Switch", 1992 IEEE ISSCC, pp. 228-229, describe a bipolar n by n crosspoint switch which requires n n:1 multiplexers. While such circuits are practically implementable in bipolar technology for reasonably small values of n (i.e., about less than n=256), such crosspoint architectures implemented in CMOS technology are not practical, since they would occupy more chip area than a fully populated matrix with one or more RAM cells used to drive each switch in the matrix as described above. In addition, in the architecture described in the Shin et al. paper, the number of crosspoints is necessarily quadratic in the number of objects (i.e., I/O pins or logic cell inputs and outputs) being switched. This attribute of this architecture severely restricts the number of objects which may be interconnected using a single reasonably sized integrated circuit die.
Time/space switch programmable architectures, such as that disclosed in S. Carpenter et al., "A 146 Mb/s Time Space Switch Chip", 1988 IEEE ISSCC, pp. 112--113, are also known in the art. The number of RAM cells used in such architectures is at least twice the number of switches being used to pass or block data at any given time.
It is an object of the present invention to provide a user re-programmable interconnect architecture in which the active switching device and its associated active storage element occupy less die area than in previous re-programmable interconnect architectures.
It is a further object of the present invention to provide a user re-programmable interconnect architecture in which N switching elements may be controlled by fewer than N active storage elements.
It is a further object of the present invention to provide a user re-programmable interconnect architecture in which N switching elements may be controlled by fewer than N active storage elements and in which a maximum number of interconnections is permitted.
It is a further object of the present invention to provide increased routability in a user re-programmable interconnect architecture through the use of non-parallel decoder lines thus increasing the number of creatable nets in a given number of switching elements.
It is a further object of the present invention to decrease the number of decoder lines required to control the switching elements to a single decoder line in each direction.
It is yet another object of the present invention to provide increased routability in a user re-programmable interconnect architecture in which N switching elements may be controlled by fewer than N active storage elements through the use of non-parallel single decoder lines and partial switch depopulation thus further increasing the number of nets creatable in a given number of switching elements.